The present invention relates to network interfacing and more particularly, to methods and systems for transferring data between a host system memory and a buffer memory in a network interface device configured for accessing Ethernet media, in a manner that employs transmit descriptors
Network interface devices handle packets of data for transmission between a host computer and a network communications system, such as a local area network. The host computer may be implemented as a client station, a server, or a switched hub. One primary function of the network interface device is to buffer data to compensate for timing discrepancies between the clock domain of the host computer and the clock domain of the network.
Network interface devices typically include a first in, first out (FIFO) buffer memory for storing transmit and receive data, where the transmit data is stored in a transmit FIFO prior to transmission on the network media by the MAC, and receive data is stored in a receive FIFO by the MAC prior to transfer to the host computer via the host computer bus interface.
One disadvantage with the use of a FIFO for a transmit buffer or a receive buffer is the increased latency encountered during the buffering process. The latency of the network interface device is the time delay between the time that a data frame is supplied to the network interface device and the time the data is transmitted on the network media, or vice versa.
An additional problem caused by the buffering of data between the clock domain of the host computer and the clock domain of the network interface device is buffer overflow or underflow. For example, buffer overflow can occur when the time domains between the host bus and the network media are uncontrollable to the extent that data is stored in the buffer at a rate faster than the data can be removed, resulting in an overflow situation. Conversely, underflow occurs if data is removed from the FIFO buffer faster than the data can be supplied.
Hence, the non-synchronous relationship between the host bus clock domain and the network clock domain have required the necessity of FIFO buffers to compensate for timing discrepancies between the host computer and the network.
Network interface devices configured for transferring data between host system memory and the FIFO buffer using DMA transfers have typically used descriptor entries, stored in system memory, to provide information needed by the DMA management unit on the network interface device to transfer either transmit data or receive data between the system memory and the network interface device. In particular, the descriptor entries are typically organized as ring structures in system memory, and include one descriptor ring for transmit data and another descriptor ring for receive data. Each descriptor entry is used to describe a single buffer. Since a frame may occupy one or more buffers, multiple descriptor entries may be used to identify multiple buffers storing data for a given data frame. Hence, for each transfer of frame data (i.e., packet data), the network interface device needs to perform two DMA transfers from system memory, namely one DMA transfer to obtain descriptor information related to the frame data, and a second DMA transfer for the actual stored frame data.
Once the DMA controller in the network interface device has read the data from the system memory, it is transmitted over the network. After the data has been transmitted, the network interface device writes status information into the transmit descriptor stored in the system memory. The central processing unit (CPU) is then interrupted to return the data buffers to the CPU. Once the data buffers have been returned, the CPU may reuse those same data buffers for new frames to be transmitted.
One of the concerns in any communication system is that of communication speed. In the above-described systems, there is a period of time that passes between the receipt of the frame data by the network interface device from the system memory until the buffers are able to be reused by the central processing unit to process a different frame. Part of this time is due to the determination of the transmission status of that frame so that the status information may be written back to the transmit descriptor, with the freeing of the buffers occurring after the transmit descriptor has been updated with the status information.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
There is a need for a method and apparatus for transferring frame data between a host system memory and a network interface buffer memory employing transmit descriptors that operates in a faster manner to return buffers to a central processing unit for re-use with different frame data.
These and other needs are met by embodiments of the present invention which provide a method of transmitting data from a node on a network comprising the steps of reading a transmit descriptor from a memory to determine the location within the memory of data to be transmitted. The data to be transmitted is copied from the memory to a network interface controller. The location in the memory of the data is freed immediately after the copying of the data to the network interface controller, regardless of any transmission of the data from the node. Attempts are then made to transmit the data on the network from the network interface controller. Various statistics counters are updated on the network interface controller with transmission status information.
The present invention recognizes that due to the manner in which upper layer network protocols operate, status information is only used for statistics purposes. Therefore, the present invention does not wait until after the frame has been transmitted before returning the buffer to the CPU for re-use. This has the effect of returning the buffers as soon as possible and speeding up operation of the arrangement. This is especially important in instances which the network is operating in a half-duplex mode since multiple collisions may cause a delay of many milliseconds before the frame is actually transmitted. In prior art arrangements, the frame must be transmitted before the buffers are returned to the CPU. Instead, the buffers are returned to the CPU in the present invention as soon as the frame data has been copied to the network interface controller.
The earlier stated means are also met by another embodiment of the present invention which provides a network interface device for transferring data frames between a host system memory and network media. The network interface device includes a buffer memory and a memory controller configured for transferring data frames between a host system memory and the buffer memory. Transmission logic is configured to transmit the data frames from the buffer memory to the network media. The network interface device also includes statistics counters configured to store transmission status information.
Since the transmit descriptors are not written back with status information regarding the transmissions frame, the status information used for statistics purposes are kept in the statistics counters on the network interface device according to the present invention. In certain embodiments, the buffer memory is sized sufficiently to store a complete maximum length data frame. This is preferred since the locations in system memory are immediately freed upon the copying of the frame to the network interface device. Since collisions may force the frame to be re-transmitted, the network interface device should have a buffer memory large enough to hold a complete maximum-length frame.
Additional objects, advantages, and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by the practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.